Coding Fun

module displayFPGA(AN, seg, rst_l, ld_enable, clk);
input clk, ld_enable, rst_l;
output reg [3:0] AN;
output reg [6:0] seg;
reg [1:0] state, next_state;
reg [15:0] count;
parameter A = 2'b10, B = 2'b11, C = 2'b01, D = 2'b00;

always @ (posedge clk or negedge rst_l)
begin
if(!rst_l)
begin
state <= A;
count <= 0;
end
else
begin
state <= next_state;
if(count < 400001)
count <= count + 1;
else
count <= 0;
end
end

always @ (posedge clk)
begin
if(ld_enable)
case(state)
A: //Anode 0
begin
AN[0] <= 0;
AN[1] <= 1;
AN[2] <= 1;
AN[3] <= 1;
seg <= 7'b0000001; //Display Zero on Anode 0
if(count == 100000)
next_state <= B;
else
next_state <= A;
end

B: //Anode 1
begin
AN[0] <= 1;
AN[1] <= 0;
AN[2] <= 1;
AN[3] <= 1;
seg <= 7'b0110000;
if(count == 200000)
next_state <= C;
else
next_state <= B;
end

C: //Anode 2
begin
AN[0] <= 1;
AN[1] <= 1;
AN[2] <= 0;
AN[3] <= 1;
seg <= 7'b0000011;
if(count == 300000)
next_state <= D;
else
next_state <= C;
end

D: //Anode 3
begin
AN[0] <= 1;
AN[1] <= 1;
AN[2] <= 1;
AN[3] <= 0;
seg <= 7'b0110000;
if(count == 400000)
next_state <= A;
else
next_state <= D;
end

endcase
else
seg <= 7'b1111110;
end

endmodule